The present invention relates to a metal nitride oxide semiconductor (MNOS) device. More particularly, the present invention relates to an MNOS device having a gate dielectric comprising a silicon nitride (hereinafter referred to simply as "SIN") film formed on the surface of a silicon oxide film.
An MNOS device comprises a double-layer structured gate dielectric composed of a silicon oxide film and an SiN film. The device is suitable for use in, for example, charge-coupled devices (CCDs). When a CCD has a gate dielectric which consists of a silicon oxide film alone, the signal charge is not always transferred smoothly because it is difficult to form the silicon oxide film with a uniform thickness, the silicon oxide film being positioned under the first transfer electrode of polysilicon and the second transfer electrode of polysilicon. Such a problem can be overcome by providing a double-layered gate dielectric comprising a silicon oxide film and a SiN film.
Accordingly, attempts have been made to provide a device having a double-layered gate dielectric comprising a silicon oxide film and an SiN film for CCDs. The insulated gate transistors as an output circuit and the like of CCDs has employed an MNOS transistor.
Referring to the cross section view of FIG. 3, the characteristics of an MNOS transistor source and drain regions is described below.
The MNOS transistor comprises a semiconductor substrate 1 having thereon a field insulating film 2, a silicon oxide film 3, and an SiN film 4. The silicon oxide film 3 and the SiN film 4 constitute a gate dielectric 5. A gate electrode 6 is formed on the SiN film 4, and a source region 7 as well as a drain region 8 are provided in the structure.
In the structure described above, the SiN film 4 provided under and in the vicinity of the gate electrode 6 is formed in such a manner that a margin of less than 1 .mu.m may be established on the outer side of the gate electrode 6 to assure a sufficiently high resistance against insulation breakdown. Furthermore, the SiN film 4 provided on the field insulating film 2 is formed in such a manner that also a margin of less than 1 .mu.m may be obtained on the region corresponding to the source region 7 and the drain region 8. FIG. 5 is a plan view showing the positional relationship of the field, the SiN film, the source S, the drain D, and the gate in a prior art MNOS transistor. The hatched portion corresponds to the portion having the SiN film thereon.
In a prior art MNOS device, however, as shown in FIGS. 6(A) and 6(B), peeling off of the film was found to occur frequently on the margin of the SiN film 4 sticking outward from the gate electrode 6 or on the marginal SiN film 4a extending from the field insulating film 2 to, for instance, the source region 7 or the drain region 8.